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DATA SHEET
MOS INTEGRATED CIRCUIT
PD161660
POWER SUPPLY FOR TFT-LCD DRIVER
DESCRIPTION
The PD161660 is a power supply IC for TFT-LCD driver. This ICs can generate the levels which TFT-LCD driver need, from 2.7 V.
FEATURES
* To generate 3 levels from single voltage input * To integrate regulator circuit for source and gate driver
ORDERING INFORMATION
Part number 5 Package Chip
PD161660P
Remark
Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14799EJ1V0DS00 (1st edition) Date Published May 2002 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
(c)
2000, 2002
PD161660
1. BLOCK DIAGRAM/SYSTEM DIAGRAM
VDC VCC1 C1 C1 C1 C1 C1 C1
C1+ C1 - C2+ C2 - C3 + C3 - C4 + C4 - C5 + C5 - C6 + C6 -
VDD1
DC/DC
C2 VCC X7 VDD2 C2 VO C1 0 V (GND) C2 VEE
VREG
VREFSEL 2.5 V VREF MVT
VREF VDD1 + - RbT RaT RcT VDD2 - VDD2 VT C3 15 V 12.5 V
MVS RbS RcS RaS
+
VS C3 FS0 FS1 LFS0 LFS1 LPM ACS0 ACS1 LACS0 LACS1 DCON RGONP VSS DVSS
5V 4V
TESTOUT TESTIN1 to TESTIN6 RSEL EXRVT EXRVS www..com VCE VCD2 VCD11 VCD12
2
Data Sheet S14799EJ1V0DS
PD161660
2. PIN CONFIGURATION (Pad Layout)
Chip size: X = 4.20 mm, Y = 4.35 mm Pad size : 100 x 100 m (1) Alignment mark
30 m 30 m 30 m
2
30 m
30 m 30 m
(2) Arrangement
DUMMY DUMMY
33
C2+
18
19
20
21
22
23
24
25
26
27
C3-
28
29
30
31
32
DUMMY
C1+
C2-
C1-
34
DUMMY VDD2 VDD1 MVT VT VREF MVS VS
DUMMY
C6+
C5+
C4+
C3+
C6-
C5-
C4-
VO
17 D161660 16 15 14 13 12 11
35 36 37 38 39 40 41
DUMMY TESTIN1 TESTIN2 TESTIN3 DUMMY VSS DUMMY VCC1 DUMMY DUMMY TESTIN4 TESTIN5 TESTOUT TESTIN6 DVSS LACS0 DUMMY
Chip Surface (Bump Side)
Y
10 9 8 7 6 5 4 3 2 1 42
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DUMMY DUMMY VDC DUMMY DUMMY VCE VCD2 VCD12 DUMMY X
43 44 45 46 47 48 49 50 51
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
RGONP
VREFSEL
EXRVS
LACS1
DCON
LPM
FS1
LFS1
LFS0
FS0
ACS1
RSEL
ACS0
DUMMY
DUMMY
VCD11
EXRVT
Alignment Mark (No Bump)
Alignment Mark (No Bump)
X = 4.20 mm
Y = 4.35 mm
Data Sheet S14799E1V0DS
3
PD161660
Table 2-1. Pad Layout
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pad name DUMMY VCD12 VCD2 VCE DUMMY DUMMY VDC DUMMY DUMMY VS MVS VREF VT MVT VDD1 VDD2 DUMMY DUMMY VO C6 C5 C4 C3
+ -
X[mm] -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1950 -1800 -1575 -1350 -1125 -900 -675 -450 -225 0 225 450 675 900 1125 1350 1575 1800 1950 1950 1950 1950 1950 1950
Y[mm] -1800 -1575 -1350 -1125 -900 -675 -450 -225 0 225 450 675 900 1125 1350 1575 1800 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 2025 1800 1575 1350 1125 900 675
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Pad name DUMMY VCC1 DUMMY DUMMY TESTIN4 TESTIN5 TESTOUT TESTIN6 DVSS LACS0 DUMMY DUMMY LACS1 VREFSEL ACS0 ACS1 RSEL FS0 FS1 LFS0 LFS1 EXRVS EXRVT DCON RGONP LPM VCD11 DUMMY
Alignment mark Alignment mark
X[mm] 1950 1950 1950 1950 1950 1950 1950 1950 1950 1950 1950 1800 1575 1350 1125 900 675 450 225 0 -225 -450 -675 -900 -1125 -1350 -1575 -1800 -1950 1950
Y[mm] 450 225 0 -225 -450 -675 -900 -1125 -1350 -1575 -1800 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025 -2025
C6 C5 C4 C3
+ -
+ -
+ -
28 C2 www..com C2- 29 30 31 32 33 34 35 36 37 38 39 40 C1
-
+
+
C1
DUMMY DUMMY DUMMY DUMMY TESTIN1 TESTIN2 TESTIN3 DUMMY VSS
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Data Sheet S14799EJ1V0DS
PD161660
3. PIN FUNCTIONS
(1/2)
Symbol VDC VCC1 VSS DVSS VDD1 Pin Name Power supply Power supply Ground Ground DC/DC converter output Pad No. 7 42 40 49 15 I/O - - - - - Description Power supply for DC/DC converter. Power supply for logic circuit. Ground. Ground (for control pin pull-down) Boost voltage of DC/DC converter (x4, x5, x6 or x7). The capacitors required for each boost level are shown below. * x4 boost: C1, C2, C6 (C3, C4, and C5 are not required) * x5 boost: C1, C2, C3, C6 (C4, and C5 are not required) * x6 boost: C1, C2, C3, C4, C6 (C5 is not required) * x7 boost: C1, C2, C3, C4, C5, C6 VDD2 DC/DC converter output 16 - Boost voltage of DC/DC converter (x2 or x3). The boost steps for VDD2 is selected by VCD2 pin. The capacitors required for each boost level are shown below. * x2 boost: C1 * x3 boost: C1, C2, VO Rectangle signal output for negative boost 19 - Rectangle signal output for negative boost. The VO voltage range is selected by VCE pin. The capacitors required for each boost level are shown below. * x3 boost: C1, C2 * x4 boost: C1, C2, C3 * x5 boost: C1, C2, C3, C4 * x6 boost: C1, C2, C3, C4, C5 * x4 boost: C1, C2, C6 * x5 boost: C1, C2, C3, C6 * x6 boost: C1, C2, C3, C4, C6
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* x7 boost: C1, C2, C3, C4, C5, C6 Regulator output Regulator output Reference voltage input/output 13 10 12 - - I/O 15 V/12.5 V regulator output for gate driver. 5 V/4 V regulator output for source driver. The gate driver includes reference voltage for VB regulator. When VREFSEL = H, external reference voltage can be input. Reference voltage input/output pin of VT, VS regulator.
VT VS VREF
DCON RGONP EXRVT EXRVS
DC/DC converter control Regulator control VT regulating resistor selection VS regulating resistor selection
64 65 63 62
I I I I
DC/DC converter ON/OFF control. Connect to DCON pin of source driver. Regulator ON/OFF control. Connect to RGONP pin of source driver. To select internal/external resistor for VT regulator. To select internal/external resistor for VS regulator.
Data Sheet S14799E1V0DS
5
PD161660
(2/2)
Symbol VCD11 VCD12 VCD2 VCE LPM Pin Name VDD1 booster selection VDD1 booster selection VDD2 booster selection VO level selection Low power mode signal Pad No. 67 2 3 4 66 I/O I I I I I Description To select x4/x5/x6/x7 boost for VDD1. Connect to VCD11 pin of source driver. To select x4/x5/x6/x7 boost for VDD1. Connect to VCD12 pin of source driver. To select x2/x3 boost for VDD2. Connect to VCD2 pin of source driver. To select x3/x4/x5/x6/x7 boost for VO top voltage level. Connect to VCE pin of source driver. Control signal for low power mode. When this pin is high level, it comes to be low power mode. LPM = H: LACS0, LACS1, LFS0, LFS1 are enabled. LPM = L : ACS0, ACS1, FS0, FS1 are enabled. Connect to LPMP pin of source driver. ACS0, ACS1 LACS0, LACS1 MVT MVS TESTIN1TESTIN6 TESTOUT FS0, FS1 Test output OSC frequency selection VT regulator input VS regulator input Test Amp. current selection Amp. current selection 55, 56 50, 53 14 11 - - I EXRVT = H: Connect to external resistor. EXRVT = L: Leave it open. EXRVS = H: Connect to external resistor. EXRVS = L: Leave it open. 36-38, 45, 46, 48 47 58, 59 60, 61 57 54 O I I I Test pin. Normally leave them open. To select OSC frequency for DC/DC converter when in scanning. LFS0, LFS1 OSC frequency selection
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I I
To select Amp. current when in scanning. To select Amp. current in low power mode.
Test pins. Normally leave it open.
To select OSC frequency for DC/DC capacitor when in scanning. To select internal resistor for regulator.
regulator VREFSEL
+ + + + + + - - - - - -
Regulator reference voltage input selection
I
To select external or internal reference voltage of VT, VS regulator.
C1 , C1 C2 , C2 C3 , C3 C4 , C4 C5 , C5 C6 , C6
Capacitor connect pin for boost
30, 31 28, 29 26, 27 24, 25 22, 23 20, 21
-
To connect external capacitor for DC/DC converter. The capacitance and tolerance of each capacitor are shown below. Capacitance : 1 F
Withstanding voltage: 10 V
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Data Sheet S14799EJ1V0DS
PD161660
4. MODE DESCRIPTION
(1) DC/DC converter control
DCON H L DC/DC converter ON DC/DC converter OFF
(2) Regulator control
RGONP H L Regulator ON Regulator OFF (VT, VS = High impedance)
(3) VT regulating resistor
EXRVT H L External resistor Internal resistor
(4) VS regulating resistor
EXRVS H L External resistor Internal resistor
(5) VDD2 booster selection
VCD2 H L x3 booster x2 booster
(6) VT, VS regulator selection
VT RSEL
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VS 5.0 V 4.0 V
H L
15.0 V 12.5 V
(7) Regulator reference voltage input selection
VREFSEL H L VREF : External reference voltage input VREF : Internal reference voltage output
Data Sheet S14799E1V0DS
7
PD161660
(8) VDD1 and VO high-level booster selection
VCD12 H H H H L L L L VCD11 H H L L H H L L VCE H L H L H L H L VDD1 booster x7 VDC x7 VDC x6 VDC x6 VDC x5 VDC x5 VDC x4 VDC x4 VDC VO high level x7 VDC x6 VDC x6 VDC x5 VDC x5 VDC x4 VDC x4 VDC x3 VDC
(9) Amp. current selection
VT ACS0
Note
VS Amp. current Source current Sink current Amp. current
ACS1
Note
Source current
Sink current
(LACS0) L L H H
(LACS1) L H L H 1 mA > 1 mA > 1 mA > 1 mA > 0.5 A 1 A 2.5 A 5 A 1 A 2 A 5 A 10 A 3 mA > 3 mA > 3 mA > 3 mA > 0.5 A 1 A 2.5 A 5 A 1 A 2 A 5 A 10 A
Note
ACS0, ACS1 : Current selection in scanning time LACS0, LACS1: Current selection in low power mode
(10) OSC frequency selection
FS1, LFS1 L L
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Note
FS0, LFS0 L H L H
Note
OSC fOSC/8 fOSC/2 fOSC/32 fOSC/256
H
Note
FS0, FS1
: Current selection when in scanning
LFS0, LFS1: Current selection in low power mode
(11) Low power mode selection
LPM H Low power mode LACS0, LACS1, LFS0, LFS1 are enable. L Normal mode ACS0, ACS1, FS0, FS1 are enable.
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Data Sheet S14799EJ1V0DS
PD161660
Figure 4-1. Example of Internal/External resistor for the regulator
VREG
VREFSEL 2.5 V VREF MVT
VREF
VREG
VREFSEL
VREG
+ -
VT C3
15 V
2.5V VREF MVT
+ -
VT C3
15 V
RbT VT VDD2 - MVS + VS C3 MVS 5V VS RaS RbS RaT - + VS VDD2
5V C3
Internal Resistor Mode EXRVT = L EXRVS = L
External Resistor Mode EXRVT = H EXRVS = H VT = (1 + RbT ) VREF
RaT
VS = (1 + RbS ) VREF
RaS
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Data Sheet S14799E1V0DS
9
PD161660
5. POWER ON/OFF SEQUENCE
5.1 Power ON sequence
VDC
2.5 V
VCC1
tVR1
0 ns 1.7 V
VCC2
0 ns
tVR2
/RESET RESET command
100 ns < 0 ns
DISP ON command
DCON tDDRP RGONP tRPRG
RGONG
tRGOE1 OE1
OE2 A B
tVR1, tVR2 = 100 ns MIN. www..com
Remarks 1. /xxx indicates active low signal. 2. OE1, OE2, /RESET, RGONG, RGONP, VCC2 are signals from source driver.
x All three power supplies, VDC, VCC1, and VCC2, can be on at the same time. y The pins are fixed to the following levels by the source driver during the period of /RESET = L (A period). Note that the gate output is fixed to the VB level, and the DC/DC converter and the regulators are off. DCON, RGONG, RGONP, OE1: L (low level) OE2: H (high level) z The /RESET pin can be made high at the end of both tVR1, which starts from the rising edge of VCC1, and tVR2, which starts from the rising edge of VCC2. { The wait time between when the /RESET signal rises and when the RESET command is acknowledged must be at least 100 ns. | The logical status of the DCON, RGONG, RGONP, OE1, and OE2 pins in the period between when the /RESET signal rises and when the RESET command (part) is acknowledged (B period) is undefined. Be aware, therefore, 10
Data Sheet S14799EJ1V0DS
PD161660
that the gate output may be undefined and the DC/DC converter and the regulators may be on. If the B period is sufficiently short however, it is unlikely that the display will be affected. Note that the gate output MAX value in the B period must be determined separately as a specification of the LCD module. The pins are re-fixed to the following levels by the source driver when the RESET command is input. Note that the gate output is fixed to the VB level, and the DC/DC converter and the regulators are off. DCON, RGONG, RGONP, OE1: L (low level) OE2: H (high level) ~ Set a timing that ensures the DCON, RGONP, and RGONG pins are shifted to high level in that order after the RESET command is input. At this time, the DC/DC converter and the regulators are on. Before that, the booster level must have been set up (by BGRS, VCE, VCD2, PVCOM of R32 register and R34 register of the PD161620) . Note that the target timing of tDDRP and tRPRG (while the DC/DC converter output and regulator output is stable) is tDDRP = approx. 50 ms and tRPRG = approx. 20 ms, but users are requested to set the final timing after sufficiently evaluating the PD161660 in the LCD module. Input the DISPON command (part) after ensuring that all the power supplies are high level. The source driver will start display with OE1 = H. The target is tRGOE1 = approx. 1 ms, but users are requested to set the final timing after sufficiently evaluating the
PD161660 in the LCD module.
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Data Sheet S14799E1V0DS
11
PD161660
5.2 Power OFF sequence
VDC
0 ns
VCC1
0 ns
VCC2
0 ns
/RESET STBY command
< 1-frame 0 ns
DCON
tRPDD
RGONP
tRGRP
RGONG
tOE2RG
OE1
OE2
Remark OE1, OE2, /RESET, RGONG, RGONP, VCC2 are the signals from driver.
x Input the STBY command (part). The source driver sets the status of the OE1 and OE2 pins to low level within one frame. The gate output www..com is fixed to VT. y Set a timing that ensures the RGONG, RGONP, and DCON pins are shifted to low level in that order after the panel load has been sufficiently discharged (tOE2RG timing; Secure an amount of time equivalent to one frame after executing the standby command). At this time, the DC/DC converter and the regulators are off. Note that a timing of 0 ns for tRGRP and tRPDD causes no problems on the device side, but users are requested to set the final timing after sufficiently evaluating the PD161660 in the LCD module. z Although it is unnecessary to input the RESET command to the source driver, for designs in which the system is reset when the power supply is turned off, make settings that ensure /RESET = L at DCON = L and subsequent timings. { All three power supplies, VDC, VCC1, and VCC2, can be off at the same time.
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Data Sheet S14799EJ1V0DS
PD161660
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply voltage Supply voltage Input voltage Input current Output voltage Output current Output current Operating ambient temperature Storage temperature Symbol VCC1 VDC VI II VDD1 IO IO2 TA Tstg Rating -0.5 to +6.0 -0.5 to + 6.0 -0.5 to VCC1 + 0.5 10 -0.5 to +40 10 10 -40 to +85 -55 to +125 Unit V V V mA V mA mA C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -40 to +85C, VSS = 0 V)
Parameter Supply voltage Supply voltage Input voltage Symbol VCC1 VDC VI MIN. 2.5 2.5 0 TYP. 2.7 MAX. 3.6 3.6 VCC1 Unit V V V
Electrical Characteristics (Unless otherwise specified, TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VSS = 0 V)
Parameter High level input voltage
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Symbol VIH VIL VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VT VT VS VS Ivcc1d Ivdcd
Condition
MIN. 0.8 VCC1
TYP.
MAX.
Unit V
0.2 VCC1 IDD1 = 300 A, 7 x Boost IDD1 = 300 A, 6 x Boost IDD1 = 300 A, 5 x Boost IDD1 = 300 A, 4 x Boost VCD2 = L, IDD2 = 1 mA VCD2 = H, IDD2 = 1 mA RSEL = H RSEL = L RSEL = H RSEL = L VCC1 = 2.7 V, DCON, RGONG, RGONP = L VDC = 2.5 V, DCON, RGONG, RGONP = L 2.25 2.5 6 VDC 5 VDC 4 VDC 3 VDC 1.8 VDC 2.7 VDC 13.5 11.25 4.5 3.6 15 12.5 5 4 7 VDC 6 VDC 5 VDC 4 VDC 2 VDC 3 VDC 16.5 13.75 5.5 4.4 5 5 2.75
V V V V V V V V V V V
Boost voltage Boost voltage Boost voltage Boost voltage Boost voltage Boost voltage Output voltage Output voltage Output voltage Output voltage
5 5
VCC1 static current VDC static current VREF voltage
A A
V
Data Sheet S14799E1V0DS
13
PD161660
[MEMO]
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Data Sheet S14799EJ1V0DS
PD161660
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
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not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14799E1V0DS
15

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